The present disclosure relates to a semiconductor structure including local interconnect structures self-aligned to gate structures and methods of manufacturing the same.
As the transistor dimensions shrink, it becomes more critical to form different device elements with accurate overlay. Especially, it is very critical to form the contacts with accurate overlay to avoid possible short or opens. Self-aligned contact formation has been proposed to address this requirement. In conventional self-aligned contact schemes, at least two separate masks are needed to define the separate patterns for gate structures and local interconnect structures. Thus, the alignment of local interconnect structures to gate structures is subject to inherent non-zero overlay variations in conventional self-alignment schemes.
For static random access memory (SRAM) devices, conventional SRAM cells use L-shaped contact structures to minimize the area. However, as the dimensions are scaled down, it becomes more difficult to print such structures. In the state-of-the-art manufacturing processes currently employed, multiple exposures are required to form the L-shaped structure. Moreover, the irregular shape of the L-shaped structure prevents use of sidewall image transfer (SIT) or directional self-assembly that are more suited to future technology nodes than conventional lithography.